Kanan Bala Ray ¹, Sushanta K. Mandal ², B. Shivalal Patro ¹

Affiliations
1 KIIT University, Bhubaneswar - 751024, Odisha, IN
2 Centurion University, Bhubaneswar - 752050, Odisha, IN

Abstract

Objective: Leakage power is the major concern of circuit designers in nano meter technology era. The objective of this work is to design a low leakage power floating gate MOS static random access memory. Methods/Statistical Analysis: The proposed design has been made using Floating Gate MOS (FGMOS) and Leakage Control Transistor (LECTOR) technique. FGMOS has been used in place of normal MOS on the conventional SRAM cell. In the LECTOR an NMOS transistor is incorporated between output and pull down the network and a PMOS transitor is incorporated between output and pull up a network. Findings: The SRAM cell has been designed and simulated in Cadence environment on 45 nm gpdk standard CMOS process technology. From the simulation results, it is found that LECTOR FGSRAM cell reduces 90.53% leakage power, 12% delay and 33.20% overall power consumption when compared to FGSRAM cell. A detailed comparison between FGSRAM cell and LECTOR FGSRAM cell performances has been reported during WRITE operation mode. Application/Improvements: It is found that hybrid technique should be added along with LECTOR to improve the parameters.

Keywords

Floating Gate SRAM, High Speed, Hybrid Techniques, LECTOR, Low Leakage Power.

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Suryasnata Tripathy ¹, Sushanta K. Mandal ², B. Shivalal Patro ¹, L. B. Omprakash ³

Affiliations
1 KIIT University, Bhubaneswar – 751024, Odisha, IN
2 CUTM, Paralakhemundi – 761211, Odisha, IN
3 KIIT University, Bhubaneswar – 751024, Odisha

Abstract

Design of a high speed magnitude comparator with minimal power consumption is essential for addressing the ever growing need of real time signal processing and data acquisition. Simultaneous optimization of speed and power constraints is the major design bottleneck associated with digital datapath design for higher word length processors. In this work, a novel architecture for 8-bit digital comparator is proposed which is directed at high speed signal processing without incurring significant power consumption. The principle of Parallelism has been successfully employed in the proposed architecture for reduction of overall power consumption without affecting the speed. The 8-bit comparator unit is realized using three different 1-bit comparator architectures proposed in this study and their performance analysis is carried out using several combinations of input vectors. The proposed topology is designed using pass transistor logic, static CMOS logic and transmission gate based logic which accounts for the improved performance metric as compared to the more commonly employed dynamic CMOS logic based designs due to relatively smaller data activity factor. The architecture is designed in 45 nm standard CMOS Process technology using Cadence EDA tool. The introduction of parallelism and use of modified 1-bit comparator topologies significantly lower the overall power consumption along with increasing the processing speed. The proposed design achieves average power dissipation of 196 nW and propagation delay of 129 pS for a power supply voltage of 1 volt. Performance metric associated with the proposed design shows a significant improvement in performance over similar architectures reported earlier in literature. Further improvement in performance can be achieved by introducing higher degree of parallelism into the proposed architectures.

Keywords

Comparator, Dynamic CMOS Logic, High Speed, Low Power, Pass Transistor Logic, Static CMOS Logic, Transmission Gate Based Logic

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